Imagine connecting thousands of powerful AI chips scattered in dozens of server cabinets and making them work together as if they were a single, massive computer. That is exactly what Huawei demonstrated at HUAWEI CONNECT 2025, where the company unveiled a breakthrough in AI infrastructure architecture that could reshape how the world builds and scales artificial intelligence systems.
Instead of traditional approaches where individual servers work somewhat independently, Huawei’s new SuperPoD technology creates what the company’s executives describe as a single logical machine made from thousands of separate processing units, allowing them, or it, to “learn, think, and reason as one.”
The implications extend beyond impressive technical specifications, representing a shift in how AI computing power can be organised, scaled, and deployed in industries.
The technical foundation: UnifiedBus 2.0
At the core of Huawei’s infrastructure approach is UnifiedBus (UB). Yang Chaobin, Huawei’s Director of the Board and CEO of the ICT Business Group, explained that “Huawei has developed the groundbreaking SuperPoD architecture based on our UnifiedBus interconnect protocol. The architecture deeply interconnects physical servers so that they can learn, think, and reason like a single logical server.”
The technical specifications reveal the scope of this achievement. The UnifiedBus protocol addresses two challenges that, historically, have limited large-scale AI computing: the reliability of long-range communications and bandwidth-latency. Traditional copper connections provide high bandwidth but only over short distances, typically connecting perhaps two cabinets.
Optical cables support longer range but suffer from reliability issues that become more problematic the greater the distance and scale. Eric Xu, Huawei’s Deputy Chairman and Rotating Chairman, said that solving these fundamental connectivity challenges was essential to the company’s AI infrastructure strategy.
Xu detailed the breakthrough solutions in terms of the OSI model: “We have built reliability into every layer of our interconnect protocol, from the physical layer and data link layer, all the way up to the network and transmission layers. There is 100-ns-level fault detection and protection switching on optical paths, making any intermittent disconnections or faults of optical modules imperceptible at the application layer.”
SuperPoD architecture: Scale and performance
The Atlas 950 SuperPoD represents the flagship implementation of this architecture, comprising of up to 8,192 Ascend 950DT chips in a configuration that Xu described as delivering “8 EFLOPS in FP8 and 16 EFLOPS in FP4. Its interconnect bandwidth will be 16 PB/s. This means that a single Atlas 950 SuperPoD will have an interconnect bandwidth over 10 times higher than the entire globe’s total peak internet bandwidth.”
The specifications are more than incremental improvements. The Atlas 950 SuperPoD occupies…
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