Chip stacking strategy is emerging as China’s innovative response to US semiconductor restrictions, but can this approach truly close the performance gap with Nvidia’s advanced GPUs? As Washington tightens export controls on cutting-edge chipmaking technology, Chinese researchers are proposing a bold workaround: stack older, domestically-producible chips together to match the performance of chips they can no longer access.
The Core Concept: Building upward instead of forward
The chip stacking strategy centres on a deceptively simple premise—if you can’t make more advanced chips, make smarter systems with the chips you can produce. Wei Shaojun, vice-president of the China Semiconductor Industry Association and a professor at Tsinghua University, recently outlined to the South China Morning Post an architecture that combines 14-nanometer logic chips with 18-nanometer DRAM using three-dimensional hybrid bonding.
This matters because US export controls specifically target the production of logic chips at 14nm and below, and DRAM at 18nm and below. Wei’s proposal works precisely at these technological boundaries, using processes that remain accessible to Chinese manufacturers.
The technical approach involves what’s called “software-defined near-memory computing.” Instead of shuffling data back and forth between processors and memory—a major bottleneck in AI workloads—this chip stacking strategy places them in intimate proximity through vertical stacking.
The 3D hybrid bonding technique creates direct copper-to-copper connections at sub-10 micrometre pitches, essentially eliminating the physical distance that slows down conventional chip architectures.
The performance claims and reality check
Wei claims this configuration could rival Nvidia’s 4nm GPUs while significantly reducing costs and power consumption. He’s cited performance figures of 2 TFLOPS per watt and a total of 120 TFLOPS. There’s just one problem: Nvidia’s A100 GPU, which Wei positions as the comparison point, actually delivers up to 312 TFLOPS—more than 2.5 times the claimed performance.
This discrepancy highlights a critical question about the chip stacking strategy’s feasibility. While the architectural innovation is real, the performance gaps remain substantial. Stacking older chips doesn’t magically erase the advantages of advanced process nodes, which deliver superior power efficiency, higher transistor density, and better thermal characteristics.
Why China is betting on this approach
The strategic logic behind the chip stacking strategy extends beyond pure performance metrics. Huawei founder Ren Zhengfei has articulated a philosophy of achieving “state-of-the-art performance by stacking and clustering chips rather than competing node for node.” This represents a fundamental shift in how China approaches the semiconductor challenge.
Consider the alternatives. TSMC and Samsung are pushing toward 3nm and 2nm processes that remain completely out of…
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